1. Field of the Invention
The present invention generally relates to an apparatus and method for digital addition used in memory array testing and more particularly relates to determining whether three or more defective bits are present in a sixty-six bit memory array.
2. Description of the Related Art
Digital addition processes provide a method for xe2x80x9ccarryingxe2x80x9d when the capacity of a column is exceeded. For example, in a decimal system for adding two numbers, when the result of addition in a column exceeds nine, a one must be carried to the next column. Also, for every column except the lowest ordered one, provision must be made for receiving a number carried from the preceding lower order column. The carry operation occurs frequently in addition.
One of the simplest forms of adders is the ripple-carry adder in which a single carry from one column to the next is provided at each level, starting with the lowest order column. Although simple, the ripple-carry adder is relatively slow because of the relatively large number of levels or stages that are required. Since the circuits of one level cannot do their operations until those of the previous level have completed theirs, the time required for addition is generally determined by the number of levels.
One technique that has been employed to expedite addition separates the function of simple addition from that of the calculation of the carry bits. Probably the most common example today is the carry look-ahead adder. A carry look-ahead adder circuitry is obtained by considering the Boolean functions that define addition and applying algebra to them. In this process, two Boolean terms are usually introduced, called generate and propagate. The carry look-ahead method of addition has been standard for many years with minor changes.
It is desirable to provide digital circuitry that is able to perform these functions as fast as possible and without using great amounts of chip space. Conventional n-bit ripple carry adder circuitry is very slow and a carry-look-ahead adder is chip real estate intensive. It is further desirable to perform a greater than or equal to three of sixty-six calculation in less than 5 nanoseconds. More specifically, it is desirable to know if three or greater bits out of sixty-six is low (e.g., is defective) because a standard memory array has sixty-four Primary Data Lines (PDL) and two redundant lines. If three or more fails occur on a word line, then the two redundant PDLs cannot be used to perform the repair of the three defects. The repair then must be performed with a redundant word line.
In view of the foregoing and other problems of the conventional methods, it is, therefore, an object of the present invention to provide a circuit for indicating a status of a plurality of input signals. The circuit may include a plurality of pre-sum circuits that receive the plurality of input signals. Each pre-sum circuit may output two pre-sum output signals. The circuit may also include a plurality of first stage circuits. Each first stage circuit may receive two pre-sum output signals and outputting two first stage output signals. The circuit may also include a plurality of second stage circuits adapted to receive the first stage output signals. Each of the second stage circuits may output second stage output signals. A final stage circuit may be adapted to receive the second stage output signals and output two final stage output signals. The two final stage output signals represent the status of the plurality of input signals.
Other objects, advantages and salient features of the invention will become apparent from the following detailed description taken in conjunction with the annexed drawings, which disclose preferred embodiments of the invention.